As opposed to planar complementary metal-oxide-semiconductor (CMOS) devices, vertical field effect transistors (VFETs) are oriented with a vertical fin channel disposed on a bottom source/drain and a top source/drain disposed on the fin channel. VFETs have been pursued as a potential device option for scaling CMOS to the 5 nanometer (nm) node and beyond.
A reduction in chip power consumption can be realized by increasing the gate length (Lgate) of transistors (as compared to nominal transistors) along non-critical paths on the chip as this reduces off current leakage. However, it is difficult to implement FETs of differing lengths in VFET architecture due to challenges in aligning the junction with the physical gate.
Thus, techniques for effectively forming VFET devices with differing Lgate would be desirable.